The present invention relates generally to memory cells and, more specifically, to methods and structure for improving electrical isolation between a memory cell transistor gate and a memory cell capacitor.
Semiconductor device geometries continue to dramatically decrease in size since such devices were first introduced several decades ago. Today""s fabrication plants are routinely producing devices having feature dimensions less than 90 nm. However, solving the problems associated with implementing new process and equipment technology while continuing to satisfy device requirements has become an ever more daunting challenge.
For example, integrating the manufacture of static-random-access-memory (SRAM) cells or other memory devices having multiple transistors with other developing fabrication technologies has been troublesome, due in part to the incompatibility between process technologies. However, the process technology incompatibilities may be mitigated by employing a 1T-SRAM cell, which employs only one transistor, in contrast to the 4 or 6 transistors employed in other memory cells. Typically, a 1T-SRAM memory cell includes a transistor having the gate connected to the memory array word line, the source connected to the memory array bit line, and the drain connected to an electrode of a capacitor. This elemental cell structure can be easily scalable, and its design and manufacture can be very cost effective. Moreover, the fabrication of 1T-SRAM cells is compatible with lower thermal budgets and other advantages of recent developments in memory device fabrication.
However, existing 1T-SRAM designs suffer from excessive step height. The step height or other high aspect ratio features of 1T-SRAM cells can complicate integration with existing processes and structures. For example, a gate extension typically passes over the capacitor structure in a 1T-SRAM cell to couple the gates of two or more transistors opposing the capacitor structure. The excessive step height of the capacitor structure renders achieving adequate step coverage when forming the gate extension over the capacitor structure difficult, if not impossible. Moreover, spacers employed to isolate the capacitor electrodes from the overlying gate extension are incapable of achieving the necessary step coverage to achieve reliable and repeatable isolation.
Accordingly, what is needed in the art is a memory cell, and method of manufacture thereof, that addresses the above-discussed issues of the prior art.
To address the above-discussed deficiencies of the prior art, the present disclosure provides a memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile, wherein the second non-planar profile comprises ends of the one of the capacitor electrodes and the insulating lining.
The present disclosure also introduces a memory array including a plurality of capacitive elements. In one embodiment, the capacitive elements each include a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over one of the first and second electrodes, and a spacer having a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the first and second electrodes and the insulating lining, The memory array also includes a passing gate extending over at least one of the plurality of capacitive elements and coupling ones of a plurality of transistors each adjacent ones of the plurality of capacitive elements.
A method of manufacturing a memory cell is also provided in the present disclosure. In one embodiment, the method includes forming a capacitor having two electrodes in an opening in a substrate, wherein termini of one of the electrodes extend over and substantially parallel to the substrate. A lining is formed over and conforming to a profile of the capacitor, the lining having termini interiorly offset from the termini of the one of the capacitor electrodes. A gate electrode extension is formed, passing over the capacitor. A spacer is also formed in the method, the spacer isolating a terminus of the one of the capacitor electrodes from the gate electrode extension, the spacer also including a protrusion conforming to a recess defined by one of the lining termini and the terminus of the one of the capacitor electrodes.
The foregoing has outlined preferred and alternative features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Additional features will be described below that further form the subject of the claims herein. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure.